Bipolar CMOS select device for resistive sense memory

ABSTRACT

A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

RELATED APPLICATIONS

This application claims priority to U.S. provisional patent application No. 61/106,821, filed Oct. 20, 2008. The entire disclosure of application No. 61/106,821 is incorporated herein by reference.

BACKGROUND

Fast growth of the pervasive computing and handheld/communication industry has generated exploding demand for high capacity nonvolatile solid-state data storage devices. Current technology like flash memory has several drawbacks such as slow access speed, limited endurance, and the integration difficulty. Flash memory (NAND or NOR) also faces significant scaling problems.

Resistive sense memories are promising candidates for future nonvolatile and universal memory by storing data bits as either a high or low resistance state. One such memory, MRAM, features non-volatility, fast writing/reading speed, almost unlimited programming endurance and zero standby power. The basic component of MRAM is a magnetic tunneling junction (MTJ). MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ. As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes more severe. Resistive RAM (RRAM) is another resistive sense memory that has a variable resistance layer that can switch between a high resistance state and a low resistance state (for example by the presence or absence of a conductive filament) by applicant of a current or voltage.

However, some yield-limiting factors must be overcome before resistive sense memory enters the production stage. One challenge is that the resistive sense memory element often requires a large current in order for writing to occur. In particular, spin torque RAM (STRAM) requires high currents at fast write speeds. MOSFET select transistors have been used in such resistive sense memories. However, the area required by the MOSFET to achieve the currents needed is large. There is a need for select devices having reduced area requirements at specified writing currents for resistive sense memories.

BRIEF SUMMARY

The present disclosure relates to a bipolar select device for resistive sense memory. In particular, the present disclosure relates to a resistive sense memory apparatus that includes a bipolar select transistor that has high drive current capability for its size. The bipolar select transistor consumes a small area and shares one contact across multiple memory cells.

One illustrative resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more completely understood in consideration of the following detailed description of various embodiments of the disclosure in connection with the accompanying drawings, in which:

FIG. 1 is a cross-sectional schematic diagram of an illustrative magnetic tunnel junction data cell;

FIG. 2 is a top view schematic diagram of an illustrative resistive sense memory device or appartus;

FIG. 3 is a cross-sectional schematic diagram of the illustrative resistive sense memory apparatus of FIG. 2 taken along line 3-3;

FIG. 4 is a cross-sectional schematic diagram of the illustrative resistive sense memory apparatus of FIG. 2 taken along line 4-4; and

FIG. 5 is a flow diagram of an illustrative method of writing to a memory unit array.

The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. The definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.

Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein.

The recitation of numerical ranges by endpoints includes all numbers subsumed within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.

As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” encompass embodiments having plural referents, unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

The present disclosure relates to a bipolar select device for resistive sense memory. In particular, the present disclosure relates to a resistive sense memory apparatus that includes a bipolar select transistor that has high drive current capability for its size. The bipolar select transistor consumes a small area and shares one contact across multiple memory cells, thus the number of electrical contacts is reduced. The bipolar select device is a complementary metal-oxide-semiconductor (CMOS) bipolar select device that can be fabricated utilizing silicon on insulator (SOI) technology. By utilizing a body bias, the metal-oxide-semiconductor field effect transistor (MOSFET) is transformed into a lateral bipolar transistor. While the present disclosure is not so limited, an appreciation of various aspects of the disclosure will be gained through a discussion of the examples provided below.

Variable resistive memory includes memory cells that switch between at least a low resistance data state and a high resistance data state by passing a write current through the resistive memory cell (i.e., resistive RAM or RRAM). In some embodiments the resistive memory cell is a phase change data cell (i.e., PCRAM) or a programmable metallization data cell (i.e., PMCRAM). In some embodiments the resistive memory is a magnetic tunnel junction such as, for example, a spin transfer torque memory cell (i.e., STRAM). These magnetic tunnel junction data cells are further described below. Semiconductor fabrication techniques can be utilized to form the resistive sense memory apparatus and arrays described herein. The terms “emitter” and “collector” are interchangeable depending on the direction current is flowing through the resistive sense memory apparatus and arrays described herein.

The resistive sense memory apparatus described herein allows bipolar electrical conduction through the device at bulk conduction transport rates, allowing higher current flow per area than conventional semiconductor transistor select devices. Thus, the area required for each resistive sense memory apparatus can be reduced and the density of the memory array is increased, as compared to conventional memory array devices. Thus the select devices described herein can be termed as either NPN or PNP devices. An NPN device can have a deep Pwell for isolation purposes and a PNP device can have a deep Nwell for isolation purposes. In either case, an oxide region can work for isolation purposes.

FIG. 1 is a cross-sectional schematic diagram of an illustrative magnetic tunnel junction data cell 10. The magnetic tunnel junction data cell 10 includes a ferromagnetic free layer 12 and a ferromagnetic reference (i.e., pinned) layer 14. The ferromagnetic free layer 12 and a ferromagnetic reference layer 14 are separated by an oxide barrier layer 13 or tunnel barrier. A first electrode 15 is in electrical contact with the ferromagnetic free layer 12 and a second electrode 16 is in electrical contact with the ferromagnetic reference layer 14. The ferromagnetic layers 12, 14 may be made of any useful ferromagnetic (FM) alloys such as, for example, Fe, Co, Ni and the insulating barrier layer 13 may be made of an electrically insulating material such as, for example an oxide material (e.g., Al₂O₃ or MgO). Other suitable materials may also be used.

The electrodes 15, 16 electrically connect the ferromagnetic layers 12, 14 to a control circuit providing read and write currents through the ferromagnetic layers 12, 14. The resistance across the magnetic tunnel junction data cell 10 is determined by the relative orientation of the magnetization vectors or magnetization orientations of the ferromagnetic layers 12, 14. The magnetization direction of the ferromagnetic reference layer 14 is pinned in a predetermined direction while the magnetization direction of the ferromagnetic free layer 12 is free to rotate under the influence of a spin torque. Pinning of the ferromagnetic reference layer 14 may be achieved through, e.g., the use of exchange bias with an antiferromagnetically ordered material such as PtMn, IrMn and others. When the magnetization orientation of the ferromagnetic free layer 12 is parallel and in the same direction of the magnetization orientation of the ferromagnetic reference layer 14 the magnetic tunnel junction is described as being in the low resistance state or “0”data state. When the magnetization orientation of the ferromagnetic free layer 12 is anti-parallel and in the opposite direction of the magnetization orientation of the ferromagnetic reference layer 14 the magnetic tunnel junction is described as being in the high resistance state or “1” data state.

Switching the resistance state and hence the data state of the magnetic tunnel junction data cell 10 via spin-transfer occurs when a current, passing through a magnetic layer of the magnetic tunnel junction data cell 10, becomes spin polarized and imparts a spin torque on the free layer 12 of the magnetic tunnel junction data cell 10. When a sufficient spin torque is applied to the free layer 12, the magnetization orientation of the free layer 12 can be switched between two opposite directions and accordingly the magnetic tunnel junction data cell 10 can be switched between the parallel state (i.e., low resistance state or “0” data state) and anti-parallel state (i.e., high resistance state or “1” data state) depending on the direction of the current.

The illustrative spin-transfer torque magnetic tunnel junction data cell 10 may be used to construct a memory device that includes multiple magnetic tunnel junction data cells in an array where a data bit is stored in magnetic tunnel junction data cell by changing the relative magnetization state of the free magnetic layer 12 with respect to the pinned magnetic layer 14. The stored data bit can be read out by measuring the resistance of the cell which changes with the magnetization direction of the free layer relative to the pinned magnetic layer. In order for the spin-transfer torque magnetic tunnel junction data cell 10 to have the characteristics of a non-volatile random access memory, the free layer exhibits thermal stability against random fluctuations so that the orientation of the free layer is changed only when it is controlled to make such a change.

FIG. 2 is a top view schematic diagram of an illustrative resistive sense memory apparatus. The resistive sense memory apparatus that includes a bipolar select device 11 electrically coupled to a plurality of resistive sense memory cells (illustrated in FIG. 3). The bipolar select device 11 can be a complementary metal-oxide-semiconductor (CMOS) bipolar select device that is fabricated utilizing silicon on insulator (SOI) technology.

Four transistors 25 are arranged in a row forming a row of transistors on the bipolar select device 11. The transistors 25 are disposed in a semiconductor substrate and can be referred to as MOSFETs. The transistors 25 are electrically isolated from each other. While the row of transistors includes four transistors 25, the row of transistors can include any number of transistors 25 or plurality of transistors 25. Forming multiple rows of transistors on a semiconductor substrate creates a resistive sense memory array, where each row of transistors are electrically isolated from each other.

Each transistor 25 is disposed on or at least partially within a semiconductor substrate 20. Each transistor 25 includes a collector contact 22 and an emitter contact 24. As described above, collector and emitter contacts are interchangeable depending on the direction of current flowing through the transistor 25. The collector contact 22 and an emitter contact 24 can also be described as a source contact and a drain contact. The collector contact 22 and an emitter contact 24 are electrically isolated from each other and separated from each other by a channel region. A gate contact 26 extends along the channel region and spans between the collector contact 22 and an emitter contact 24.

A base contact 30 is disposed within the semiconductor substrate 20. The illustrated base contact 24 extends from the surface of the semiconductor substrate 20 to a base contact layer (see FIG. 3) that is buried within the semiconductor substrate 20. The base contact 30 allows the particular transistor 25 to be body biased and allow the transistor 25 to effectively turn into a lateral bipolar transistor.

FIG. 3 is a cross-sectional schematic diagram of the illustrative resistive sense memory device of FIG. 2 taken along line 3-3. This cross-section is taken through a transistor 25. The transistor 25 includes a collector contact 22 and an emitter contact 24. As described above, collector and emitter contacts are interchangeable depending on the direction of current flowing through the transistor 25.

The collector contact 22 and an emitter contact 24 are electrically isolated from each other and separated from each other by a channel region 23. A gate contact 26 extends along the channel region 23 and spans between the collector contact 22 and an emitter contact 24. A gate contact insulator layer 27 electrically isolates the gate contact 26 from the semiconductor substrate 20, as is known in MOSFET construction. The collector contact 22 and an emitter contact 24 can be regions of the semiconductor substrate 20 that are doped with an N type or P type conductivity material.

A source line SL is illustrated as being electrically coupled to the collector contact 22 and a resistive sense memory cell 10 and a bit line BL is illustrated as being electrically coupled to the emitter contact 24. In some embodiments a source line SL is electrically coupled to the emitter contact 24 and a resistive sense memory cell 10 and a bit line BL is electrically coupled to the collector contact 22.

The base contact 30 is disposed within the semiconductor substrate 20. The base contact 30 is arranged such that the emitter contact 24 and the collector contact 24 are between the base contact 30 and the gate contact 26. The base contact 30 is spaced apart from the emitter contact 24 and the collector contact 24. The base contact 30 is a common base contact for the row of transistors and the base contact 30 extends along the length of the row of transistors. In many embodiments, the gate contact 26 and the base contact 30 are co-extensive along a length of the row of transistors forming the bipolar select device 11.

When the collector contact 22 and the emitter contact 24 are doped with an N type conductivity material the base contact is doped with a high level of P type (P+) type conductivity dopant material. When the collector contact 22 and the emitter contact 24 are doped with a P type conductivity material the base contact is doped with a high level of N type (N+) type conductivity dopant material. A lightly doped region or layer 31 separates the collector contact 22 and the emitter contact 24 from the base contact 30. The lightly doped region or layer 31 has the same conductivity type as the base contact 30, but with a lower lever of doping (e.g., P or P− or N or N−). The lightly doped region or layer 31 and the base contact 30 are electrically isolated by an insulating material 28 encompassing the lightly doped region or layer 31 and the base contact 30. The insulating material 28 can be any useful electrically insulating material such as, an oxide, for example.

Applying a forward bias through the resistive sense memory cell 10 and the bipolar select device 11 writes a first or low resistance data state to the resistive sense memory cell 10. Applying a reverse bias through the resistive sense memory cell 10 and the bipolar select device 11 writes a second or high resistance data state to the resistive sense memory cell 10. By utilizing a body bias (on the base contact 30), the metal-oxide-semiconductor field effect transistor (MOSFET) is transformed into a lateral bipolar transistor.

FIG. 4 is a cross-sectional schematic diagram of the illustrative resistive sense memory apparatus of FIG. 2 taken along line 4-4. The lightly doped region or layer 31 and the base contact 30 are illustrated as being co-extensive along a length of the bipolar select device. The gate contact insulator layer 27 electrically isolates the gate contact 26 from the semiconductor substrate 20, as is known in MOSFET construction.

Insulating material 28 encompassing the lightly doped region or layer 31 and the base contact 30. The insulating material 28 isolates the transistors 25 from each other along the row of transistors of the bipolar select device. The insulating material 28 can be any useful electrically insulating material such as, an oxide, for example.

FIG. 5 is a flow diagram of an illustrative method of writing to a memory unit array 100. The method includes providing a bipolar resistive sense memory (RSM) apparatus as described above, at block 101. Then the method includes writing a first data state (i.e., low resistance state) to a plurality of resistive sense memory cells by applying a forward bias across an transistor of a bipolar select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to at block 102.

Alternatively the method includes writing a second data state (i.e., high resistance state) to a plurality of resistive sense memory cells by applying a reverse bias across a transistor of a bipolar select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to at block 103. The forward bias condition places one or more resistive sense memory cells in the low resistance state at block 104 and reverse bias condition places one or more resistive sense memory cells in the high resistance state at block 105. By utilizing a body bias (on the base contact), the metal-oxide-semiconductor field effect transistor (MOSFET) is transformed into a lateral bipolar transistor.

Thus, embodiments of the BIPOLAR CMOS SELECT DEVICE FOR RESISTIVE SENSE MEMORY are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow. 

What is claimed is:
 1. A resistive sense memory apparatus comprising: a bipolar select device comprising: a semiconductor substrate; a plurality of field effect transistors disposed in the semiconductor substrate and forming a row of field effect transistors, each field effect transistor comprising an emitter contact and a collector contact, wherein each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other, a gate contact layer extends along a channel region between the emitter contact and a collector contact; a base contact layer is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact layer and the base contact layer, the base contact layer extends along a length of the row of field effect transistors and provides a body bias to each field effect transistor in the row of field effect transistors at the same time; and a plurality of resistive sense memory cells, wherein one of the plurality of resistive sense memory cells is electrically between one of the collector contacts or emitter contacts and a bit line.
 2. A resistive sense memory apparatus according to claim 1, wherein the collector contacts and the emitter contacts have N type conductivity and the base layer has P+ type conductivity.
 3. A resistive sense memory apparatus according to claim 2, wherein each field effect transistor further comprises a layer of P− type conductivity separating the base layer from the collector contacts and the emitter contacts.
 4. A resistive sense memory apparatus according to claim 1, wherein the collector contacts and the emitter contacts have P type conductivity and the base layer has N+ type conductivity.
 5. A resistive sense memory apparatus according to claim 4, wherein each field effect transistor further comprises a layer of N− type conductivity separating the base layer from the collector contacts and the emitter contacts.
 6. A resistive sense memory apparatus according to claim 1, wherein the resistive sense memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.
 7. A resistive sense memory apparatus according to claim 1, wherein the gate contact layer is a common gate contact layer for the row of field effect transistors and extends along a length of the row of field effect transistors and the common gate contact layer is co-extensive with the base contact layer along a length of the row of field effect transistors.
 8. A resistive sense memory apparatus according to claim 1, further comprising a plurality of bipolar select devices, wherein each bipolar select device forms a row of a memory array.
 9. A resistive sense memory apparatus according to claim 8, wherein each bipolar select device is electrically isolated from each other.
 10. A resistive sense memory array, comprising: a plurality of bipolar select devices, each bipolar select device forming a row of a memory array, each bipolar select device comprising: a semiconductor substrate; a plurality of field effect transistors disposed in the semiconductor substrate and forming a row of field effect transistors, each field effect transistor comprising an emitter contact and a collector contact, wherein each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other, a gate contact layer extends along a channel region between the emitter contact and a collector contact, the gate contact layer is a common gate contact layer for the row of field effect transistors and extends along a length of the row of field effect transistors; a base contact layer is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact layer and the base contact layer, the base contact layer extends along a length of the row of field effect transistors and provides a body bias to each field effect transistor in the row of field effect transistors at the same time, and the gate contact layer is co-extensive with the base contact layer along a length of the row of field effect transistors; and a plurality of resistive sense memory cells, wherein one of the plurality of resistive sense memory cells is electrically between one of the collector contacts or emitter contacts and a bit line.
 11. A resistive sense memory array according to claim 10, wherein each bipolar select device is electrically isolated from each other.
 12. A resistive sense memory array according to claim 10, wherein the resistive sense memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.
 13. A resistive sense memory array according to claim 10, further comprising a plurality of bipolar select devices, wherein each bipolar select device forms a row of a memory array.
 14. A resistive sense memory array according to claim 10, wherein the collector contacts and the emitter contacts have N type conductivity and the base layer has P+ type conductivity and each field effect transistor further comprises a layer of P− type conductivity separating the base layer from the collector contacts and the emitter contacts.
 15. A resistive sense memory array according to claim 10, wherein the collector contacts and the emitter contacts have P type conductivity and the base layer has N+ type conductivity and each field effect transistor further comprises a layer of N− type conductivity separating the base layer from the collector contacts and the emitter contacts.
 16. A method, comprising: writing a first data state to a plurality of resistive sense memory cells by applying a forward bias across a bipolar CMOS select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to, wherein the bipolar CMOS select device comprises: a semiconductor substrate; a plurality of field effect transistors disposed in the semiconductor substrate and forming a row or transistors, each field effect transistor comprising an emitter contact and a collector contact, wherein each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other, a gate contact layer extends along a channel region between the emitter contact and a collector contact; a base contact layer is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact layer and the base contact layer, the base contact layer extends along a length of the row of field effect transistors and provides a body bias to each field effect transistor in the row of field effect transistors at the same time.
 17. A method according to claim 16, further comprising writing a second data state to a plurality of resistive sense memory cells by applying a reverse bias across bipolar CMOS select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to.
 18. A method according to claim 16, wherein the gate contact layer is a common gate contact layer for the row of transistors and extends along a length of the row of transistors and the gate contact layer is co-extensive with the base contact layer along a length of the row of transistors. 